A 71-76-GHz Receiver Frontend in 130-nm CMOS
To-Po Wang
To-Po Wang, Department of Electronic Engineering and Graduate Institute of Computer and Communication Engineering, National Taipei University of Technology, Taipei, Taiwan.
Manuscript received on May 10, 2014. | Revised Manuscript Received on May 12, 2014. | Manuscript published on May 18, 2014. | PP:15-18 | Volume-1, Issue-6, May 2014.
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A 71-76-GHz receiver frontend with a variable gain range of 48.6 dB is proposed in this paper. The receiver frontend composes of a low-noise amplifier (LNA) and a variable-gain low-noise amplifier (VG-LNA). To achieve high gain and low noise figure, the LNA consists of two common-source stages, and the VG-LNA consists of five common-source stages. Moreover, the gate terminals of the MOSFETs are adjusted to varying the frontend’s gain in this work. Based on these methods, a 71-76-GHz receiver frontend has been designed in 130-nm CMOS process. Simulated results confirm these methods applied to this receiver frontend can effectively achieve a high gain of 21 dB at 74 GHz, a variable gain range of 48.6 dB, a minimum noise figure of 6.2 dB at 71 GHz, an input-referred third-order intercept point (IIP3) of -11.0 dBm. In addition, the receiver frontend is with low supply voltage of 1.3 V.
Keywords: Low-noise amplifier (LNA), millimeter-wave (mm-wave), variable-gain low-noise amplifier (VG-LNA),