A Comparative Study of Back Gate Misalignment Effects for Nano Scale Symmetric and Asymmetric Double Gate Mosfets
Ralesh Ranjan Biswal1, Pradipta Dutta2
1Mr. Ralesh Ranjan Biswal, Electronics and Communication Engineering, KIIT University, Bhubaneswar, Odisha, India.
Mr. Pradipta Dutta, Asst. Prof. Electronics and Communication Engineering, KIIT University, Bhubaneswar, Odisha, India.
Manuscript received on May 08, 2015. | Revised Manuscript received on May 24, 2015. | Manuscript published on May 31, 2015. | PP: 37-42 | Volume-2 Issue-6, May 2015. | Retrieval Number: F0306052615
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The technical advancement in the field of device scaling leads to a major concern i.e. short channel effects in conventional single gate (SG) Metal- Oxide-Semiconductor Field-Effect-Transistor (MOSFET). Hence the double gate (DG) MOSFETs become a best option due to its better controllability of gate over the both the front and back channel. Primarily there are two types of DG-MOSFETs, known as Symmetric DG-MOSFET and Asymmetric DG-MOSFET. But the misalignment of top gate and bottom gate is a matter of concern in the fabrication process of the device. This misalignment of both the gates can cause damage to the device characteristics and affect the parameters like threshold voltage, drain current and surface potential. In this paper the back gate misalignment effects are investigated for both symmetric and asymmetric DG-MOSFETs and a comparative study has been made. The misalignment is considered towards both source side and drain side. Quantum mechanical effect and mobility degradation are not incorporated in our work for simplicity purpose.
Keywords: DG MOSFET, Gate Misalignment, Threshold voltage roll off, Drain current degradation, Surface potential variation.