Hardware Implementation of 64 Bit Floating Point Arithmetic Using VHDL
Vibha Mishra1, Vinod Kapse2

1Vibha Mishra, M Tech (Embedded System & VLSI Design) GGITS, Jabalpur, India.
2Vinod Kapse, Head (E &Communications) GGITS, Jabalpur, India.
Manuscript received on February 05, 2014. | Revised Manuscript Received on February 09, 2014. | Manuscript published on February 18, 2014. | PP: 01-04 | Volume-1, Issue-3, February 2014. | Retrieval Number: C0122021314
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Many of the scientific applications rely on floating point (FP) computation, often requiring the use of the 64 bit Floating Point format specified by the IEEE standard 754. The use of double precision (D.P.) data type improves the accuracy and dynamic range of the computation, but simultaneously it increases the complexity and performance of the arithmetical computation of the module. The design of high performance 64- Bit floating point units (FPUs) is thus of interest in this Document.
Keywords: IEEE, (D.P.) (FP).